1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a method for improving interlayer dielectric to metal adhesion.
2. Background Information
As semiconductor devices become more complex and the density of devices increases, the number of metal lines and/or metal layers used to interconnect such devices have also increased. In order to maintain and improve the electrical reliability of these devices the processes used to combine-dielectric and the metal layers must also improve. One problem that affects the electrical reliability of the metal layers is the adhesion between the interlayer dielectric and the metal layer. Poor interlayer dielectric to metal adhesion could lead to delamination. Delamination occurs when the interlayer dielectric and metal layer peel apart or separate. Delamination may cause problems when forming, filling, and electrically contacting a metal line. Thus, in the manufacture of semiconductor devices, it is important to have good interlayer dielectric to metal adhesion.
FIG. 1a illustrates a portion of a semiconductor device 100 having a metal stack 120 overlying a substrate 110 which is electrically connected to metal layer 140 via contact 130. Metal stack 120 is made up of a barrier layer 121, a metal layer 122, and an antireflective coating (arc layer) 123. Interlayer dielectric (ILD) 150 separates metal stack 120 from metal layer 140. Contact 130 is formed through ILD 150 to electrically connect metal stack 120 to metal layer 140. As shown in FIG. 1a, ILD 150 exhibits good adhesion to both metal stack 120 and to metal layer 140, thus the electrical reliability of the interconnection between stack 120 and metal layer 140 is very good.
Delamination of the ILD from the metal layer however, may occur for several reasons. One reason that delamination occurs may be the processing which the metal stack 120 is exposed to prior to the deposition of the ILD 150. For example, resist removal and wet etch techniques may leave potential contaminants and/or residues on the top surface and sidewalls of metal stack 120. Such contaminants and/or residues may degrade the adhesiveness between the metal stack and the ILD thus causing delamination to occur.
Another reason delamination occurs may be the difference in stresses of the two materials. Metal layers tend to be tensile films at room temperature. Tensile films push out on themselves, such that they tend to expand or take up the maximum molecular space. ILDs, which are generally oxides, tend to be compressive films. Compressive films pull inward on themselves, such that they tend to bind together or contract to take up the minimum molecular space. These stresses play on one another and affect the ILD to metal adhesion.
One way in which stresses may play a part in delamination has to do with the thicknesses of the metal layers and oxide layers. High density electronic circuits require multiple metal layers to complete the interconnects between transistors. Usually a metal layer required to carry a high current is thicker than a metal layer which is required to carry a lower current. In other words, the higher the current the thicker the metal layer. However, as the metal layers become thicker the ILD becomes comparatively thinner in order to maintain low contact resistance between subsequent metal layers. Thus, the stresses between a thick tensile metal film and a thin compressive ILD film provide an opportunity for delamination to occur.
Another way in which stresses may play a part in delamination is that subsequent processing steps performed after forming the metal layer and the ILD may include a heat cycle. During a heat cycle the entire wafer or a portion of the wafer may be heated. The rise in temperature may cause the metal layer to change from a tensile film into a compressive film. The ILD is already a compressive film, so as the metal film becomes compressive during heating the ILD layer and metal layer may pull (or peel) apart.
FIG. 1b illustrates one type of delamination that occurs during subsequent processing of the semiconductor device portion 100 illustrated in FIG. 1a. During a subsequent processing step, ILD 150 and metal stack 120 peel away from one another, thereby forming open 160. As shown in FIG. 1b, as ILD 150 and metal stack 120 peel away from one another, the contact 130 also lifts away from metal stack 120 thereby breaking the electrical connection between metal stack 120 and metal layer 140. Contact 130 may lift away from metal stack 120 due to a greater adhesion between contact 130 and ILD 150 than between contact 130 and metal stack 120. It should be noted that the contact 130 will stay with whichever metal layer has the most adhesion and will pull from the other.
FIG. 1c illustrates a similar delamination effect with the exception that ILD 150 has pulled away from metal layer 140 forming open 165. As ILD 150 and metal stack 120 peel away from one another, the contact 130 is also pulled away from metal layer 140 thereby breaking the electrical connection between the two metal layers. It should be noted that the delamination effect illustrated in FIG. 1c occurs mainly when the contact 130 and metal layer 140 are made from different materials or are made at separate times. One prior art technique which is used to solve the this type of delamination problem is to fill contact 130 at the same time that metal layer 140 is formed and with the same material. By filling the contact and forming the metal layer simultaneously, the contact 130 and metal layer 140 become one unit and will not pull away from one another. However, this does not solve the problem with respect to the delamination effect illustrated in FIG. 1b, wherein the delamination effect causes contact 130 to pull away from metal stack 120.
Another problem may occur with delamination before the formation of contact 130 and metal layer 140. As illustrated in FIG. 1d, delamination occurred when ILD 150 and metal stack 120 pulled away from one another forming opens 168 and 169, respectively. Thus when a via is etched in ILD 150 in order to form a contact 130 the vertical sidewalls of the via do not come directly in contact with metal stack 120. As shown in FIG. 1d, opens 168 and 169 are problematic when using a metal reflow technique to fill contact 130. Metal reflow techniques commonly use a wetting layer to aid the flow of the metal into the via. However, when wetting layer 170 is deposited, the vertical sidewalls and bottom surface of the via are coated, but because of opens 168 and 169 there is a break in wetting layer 170 between the sidewalls and the bottom such that wetting layer 170 is not continuous. Since wetting layer 170 is not continuous, when performing the metal reflow the metal flows into the via and stops at the break in wetting layer 170 causing a void to form at the bottom of contact 130. Void formation may degrade or even completely inhibit the electrical reliability of the contact.
It should also be noted that delamination may also occur where there are no contacts or plugs. In other words, delamination may occur wherever a metal layer contacts an ILD layer. Such delamination may lead to metal extrusions, shorts, and reliability failures when subjected to thermal heat cycling or are maintained at elevated operating temperatures for an extended time.
Another prior art method used to combat the problem of delamination in contact formation is the use of anchored vias, as is illustrated in FIG. 2a. FIG. 2a illustrates a portion of a semiconductor device 200 with an ILD 250 formed above a metal stack 220 and substrate 210. When forming a via the ILD is overetched in order to etch into the metal layer 222. After overetching, a clean is performed to remove the etchant, however, the via is overcleaned in order to remove a little more of metal layer 222 without removing any more of ARC layer 223, thereby forming rivets 231 and 232. The via is then filled to form anchored contact 230. Rivets 231 and 232, hold the anchored contact 230 and metal stack 220 together such that delamination may not pull anchored contact 230 from metal stack 220.
It should be noted and it will be obvious to one with ordinary skill in the art that anchored vias may generally only be used when the via is filled using chemical vapor deposition (CVD) techniques and not reflow metal techniques. CVD techniques, for example CVD tungsten techniques, allow rivets 231 and 232 to be filled because CVD techniques do not depend upon the continuity of a wetting layer to deposit the fill material into the bottom and rivets of the via. Reflow metal techniques, however, as described earlier with respect to FIG. 1d, require a continuous wetting layer in order to aid the flow of the metal into the bottom of the via. Thus, reflow metal techniques would not be able to fill rivets 231 and 232 and would leave a void in the bottom of anchored contact 230.
Another disadvantage to using anchored vias is that the etch and cleaning processes are very hard to control. In other words, it is hard to determine how long to leave the etchant and/or cleaning solution in the via in order to form the desired rivets. It is also hard to determine how quickly the etchant and/or cleaning solution should be removed. If the etchant and/or cleaning solution are not removed promptly or completely the etch process may continue to a point that may degrade device performance.
An additional disadvantage to the use of anchored vias is that the lower portion of contact 230 is anchored into metal stack 220, however the top portion of contact 230 is not anchored. Thus, as illustrated in FIG. 2b, if delamination occurs the contact 230 and metal layer 240 may still pull away from one another, forming an open 265.
Thus, what is needed is a method for improving ILD to metal layer adhesion in the formation of semiconductor devices.